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184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL 256mb ddr sdram module unbuffered 184pin dimm (32mx64 based on 32mx8 ddr sdram) 64-bit non-ecc/parity revision 0.1 november. 2001
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL revision history revision 0 (oct 2001) 1. first release for internal usage revision 0.1 (nov. 2001) 1. added ddr333 function 2. updated ddr333 test specification 3. deleted typical current in idd spec. table 4. included address and control input setup/hold time(tis/tih) at slow slew rate in ddr200/266 ac specification 5. deleted exit self refresh to write command(txsw) in ddr200/266 ac specification 6. changed unit of tmrd from tck to ns at ddr333 7. rename txsa(exit self refresh to bank active command) to txsnr(exit self refresh to non read command) at ddr200/266 8. rename txsr(exit self refresh to read command) to txsrd at ddr200/266 9. rename twpreh(dqs in hold time) to twpre at ddr200/266 10. rename tref(refresh interval time) to trefi at ddr200/266
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL general description pin description * these pins are not used in this module. pin name function a0 ~ a1 2 address input (multiplexed) ba0 ~ ba1 bank select address dq0 ~ dq63 data input/output dqs0 ~ dqs7 data strobe input/output ck0, ck0 ~ ck2, ck2 clock input cke0 clock enable input cs0 chip select input ras row address strobe cas column address strobe we write enable dm0 ~ dm7 data - in mask vdd power supply (2.5v) vddq power supply for dqs(2.5v) vss ground vref power supply for reference v ddspd serial eeprom power supply ( 2.3v to 3.6v ) sda serial data i/o scl serial clock sa0 ~ 2 address in eeprom vddid vdd identification flag nc no connection pin configurations (front side/back side) pin front pin front pin front pin back pin back pin back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 vref dq0 vss dq1 dqs0 dq2 vdd dq3 nc nc vss dq8 dq9 dqs1 vddq ck1 /ck1 vss dq10 dq11 cke0 vddq dq16 dq17 dqs2 vss a9 dq18 a7 vddq dq19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 a5 dq24 vss dq25 dqs3 a4 vdd dq26 dq27 a2 vss a1 *cb0 *cb1 vdd *dqs8 a0 *cb2 vss *cb3 ba1 dq32 vddq dq33 dqs4 dq34 vss ba0 dq35 dq40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 vddq /we dq41 /cas vss dqs5 dq42 dq43 vdd */cs2 dq48 dq49 vss /ck2 ck2 vddq dqs6 dq50 dq51 vss vddid dq56 dq57 vdd dqs7 dq58 dq59 vss nc sda scl 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 vss dq4 dq5 vddq dm0 dq6 dq7 vss nc nc *a13 vddq dq12 dq13 dm1 vdd dq14 dq15 * cke1 vddq *ba2 dq20 a12 vss dq21 a11 dm2 vdd dq22 a8 dq23 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 vss a6 dq28 dq29 vddq dm3 a3 dq30 vss dq31 *cb4 *cb5 vddq ck0 /ck0 vss *dm8 a10 *cb6 vddq *cb7 vss dq36 dq37 vdd dm4 dq38 dq39 vss dq44 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 /ras dq45 vddq /cs0 * /cs1 dm5 vss dq46 dq47 */cs3 vddq dq52 dq53 nc vdd dm6 dq54 dq55 vddq nc dq60 dq61 vss dm7 dq62 dq63 vddq sa0 sa1 sa2 vddspd samsung electronics co., ltd. reserves the right to change products and specifications without notice. key key M368L3223CTL ddr sdram 184pin dimm 32mx64 ddr sdram 184pin dimm based on 32mx8 the samsung M368L3223CTL is 32 m bit x 64 double data rate sdram high density memory modules based on 4th gen of 256 mb ddr sdram respectively. the samsung M368L3223CTL consists of eight cmos 32 m x 8 bit with 4banks double data rate sdrams in 66pin tsop-ii(400mil) packages mounted on a 184pin glass-epoxy substrate. four 0.1uf decoupling capacitors are mounted on the printed circuit board in parallel for each ddr sdram. the M368L3223CTL is dual in-line memory modules and inten-ded for mounting into 184pin edge connector sockets. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges of dqs. range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory sys- tem applications. ? p erformance range ? power supply : vdd: 2.5v 0.2v, vddq: 2.5v 0.2v ? double-data-rate architecture; two data transfers per clock cycle ? bidirectional data strobe(dqs) ? differential clock inputs(ck and ck ) ? dll aligns dq and dqs transition with ck transition ? programmable read latency 2, 2.5 (clock) ? programmable burst length (2, 4, 8) ? programmable burst type (sequential & interleave) ? edge aligned data output, center aligned data input ? auto & self refresh, 7.8us refresh interval(8k/64ms refresh) ? serial presence detect with eeprom ? pcb : height 1250 (mil) , double sided component part no. max freq. interface M368L3223CTL-c(l)b3 167mhz(6.0ns@cl=2.5) sstl_2 M368L3223CTL-c(l)a2 133mhz(7.5ns@cl=2) M368L3223CTL-c(l)b0 133mhz(7.5ns@cl=2.5) M368L3223CTL-c(l)a0 100mhz(10ns@cl=2) feature
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL functional block diagram dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0 i/o 5 i/o 4 i/o 3 i/o 2 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 i/o 5 i/o 4 i/o 3 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 i/o 5 i/o 4 i/o 3 i/o 2 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 i/o 5 i/o 4 i/o 3 i/o 2 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4 i/o 5 i/o 4 i/o 3 i/o 2 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 i/o 5 i/o 4 i/o 3 i/o 2 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 i/o 5 i/o 4 i/o 3 i/o 2 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 i/o 5 i/o 4 i/o 3 i/o 2 dm7 a0 - a13 a0-a13: sdrams d0 - d7 ras ras : sdrams d0 - d7 cas cas : sdrams d0 - d7 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d7 cs 0 cs cs cs cs cs cs cs cs ba0 - ba1 ba0-ba1: sdrams d0 - d7 dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6 dqs6 dqs7 dq15 i/o 2 dqs dqs dqs dqs notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/ cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq strap in (vss): vdd 1 vddq. *clock net wiring card edge dram1 cap dram3 cap dram5 cap r=120 w *(cap) cap will replace dram3 *if two drams are loaded, * clock wiring clock input sdrams ck0/ ck0 ck1/ ck1 ck2/ ck2 2 sdrams 3 sdrams 3 sdrams a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d7 d0 - d7 v dd /v ddq d0 - d7 d0 - d7 vref v ddid strap: see note 4 v ddspd spd
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd -1.0 ~ 3 .6 v voltage on v ddq supply relative to vss v ddq - 1 . 0 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 12 w short circuit current i os 50 ma permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : power & dc operating conditions (sstl_2 in/out) notes 1. includes 25mv margin for dc offset on v ref , and a combined total of 50mv margin for all ac noise and dc offset on v ref , bandwidth limited to 20mhz. the dram must accommodate dram current spikes on v ref and internal dram noise coupled to v ref , both of which may result in v ref noise. v ref should be de-coupled with an inductance of 3nh. 2.v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. the ac and dc input specifications are relative to a vref envelop that has been bandwidth limited to 200mhz. 5. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. 6. these charactericteristics obey the sstl-2 class ii standards. recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 70 c) parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v) v dd 2.3 2.7 i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref vddq/2-50mv vddq/2+50mv v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v 4 input logic low voltage v il (dc) -0.3 v ref -0.15 v 4 input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.3 v ddq +0.6 v 3 input crossing point voltage, ck and ck inputs v ix (dc) 1.15 1.35 v 5 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver) ;v out = v tt + 0.84v i oh -16.8 ma output high current(normal strengh driver) ;v out = v tt - 0.84v i ol 16.8 ma output high current(half strengh driver) ;v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver) ;v out = v tt - 0.45v i ol 9 ma
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL ddr sdram spec items and test conditions conditions symbol operating current - one bank active-precharge; trc=trcmin; dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle idd0 operating current - one bank operation ; one bank open, bl=4, reads - refer to the following page for detailed test condition idd1 percharge power-down standby current; all banks idle; power - down mode; cke = =vih(min);all banks idle; cke > = vih(min); address and other control inputs changing once per clock cycle; vin = vref for dq,dqs and dm idd2f precharge quiet standby current; cs# > = vih(min); all banks idle; cke > = vih(min); address and other control inputs stable with keeping >= vih(min) or == vih(min); cke>=vih(min); one bank active; active - precharge; trc=trasmax; dq, dqs and dm inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle idd3n operating current - burst read; burst length = 2; reads; continguous burst; one bank active; address and control inputs changing once per clock cycle; 50% of data changing at every burst; lout = 0 m a idd4r operating current - burst write; burst length = 2; writes; continuous burst; one bank active address and control inputs changing once per clock cycle; dq, dm and dqs inputs changing twice per clock cycle, 50% of input data changing at every burst idd4w auto refresh current; trc = trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz and 12*tck for ddr333; distributed refresh idd5 self refresh current; cke =< 0.2v; external clock should be on; tck = 100mhz for ddr200, 133mhz for ddr266a & ddr266b and 166mhz for ddr333 idd6 orerating current - four bank operation ; four bank interleaving with bl=4 -refer to the following page for detailed test condition idd7a recommended operating conditions unless otherwise noted, t a =0 to 70 c )
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL ddr sdram i dd spec table * module i dd was calculated on the basis of component i dd and can be differently measured according to dq loading cap. symbol b3(ddr333@cl=2.5) a2(ddr266@cl=2) b0(ddr266@cl=2.5) a0(ddr200@cl=2) unit notes idd0 840 760 680 ma idd1 1120 1000 960 ma idd2p 24 24 24 ma idd2f 256 216 184 ma idd2q 160 144 128 ma idd3p 320 256 240 ma idd3n 480 400 360 ma idd4r 1480 1240 1080 ma idd4w 1360 1120 960 ma idd5 1560 1360 1200 ma idd6 normal 24 24 24 ma low power 12 12 12 ma optional idd7a 2800 2360 1920 ma < detailed test conditions for ddr sdram idd1 & idd7a > idd1 : operating current: one bank operation 1. only one bank is accessed with trc(min), burst mode, address and control inputs on nop edge are changing once per clock cycle. lout = 0ma 2. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=4, trcd = 2*tck, tras = 5*tck read : a0 n r0 n n p0 n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl=2, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - ddr333(166mhz, cl=2.5) : tck=6ns, cl=2.5, bl=4, trcd=10*tck, tras=7*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL ac operating conditions parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals vih(ac) vref + 0.31 v 3 input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.31 v 3 input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2 note 1. vid is the magnitude of the difference between the input level on ck and the input on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. 3. these parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula - tion. the ac and dc input specificatims are refation to a vref envelope that has been bandwidth limited 20mhz. i dd7a : operating current: four bank operation 1. four banks are being interleaved with trc(min), burst mode, address and control inputs on nop edge are not changing. lout = 0ma 2. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=4, trrd = 2*tck, trcd= 3*tck, read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 a0 r3 a1 r0 - repeat the same timing with random address changing *100% of data changing at every burst - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5, bl=4, trrd = 2*tck, trcd = 3*tck read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing *100% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl2=2, bl=4, trrd = 2*tck, trcd = 3*tck,read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing *100% of data changing at every burst -ddr333(166mhz,cl=2.5) : tck=6ns, cl=2.5, bl=4, trrd=2*tck, trcd=3*tck,read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing *100% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL output load circuit (sstl_2) output z0=50 w c load =30pf v ref =0.5*v ddq r t =50 w v tt =0.5*v ddq input/output capacitance (v dd = 2 . 5 v, v ddq =2.5v, t a = 25 c , f=1mhz) parameter symbol min max unit input capacitance(a 0 ~ a 1 2 , ba 0 ~ ba 1 , ras , cas , we ) c in1 49 57 pf input capacitance(cke 0 ) c in2 42 50 pf input capacitance( cs 0 ) c in3 42 50 pf input capacitance( clk 0 , clk 1 , clk 2 ) c in4 22 25 pf data & dqs input/output capacitance(dq 0 ~dq 63 ) c out 6 8 pf input capacitance(dm 0 ~dm 8 ) c in5 6 8 pf ac operating test conditions (v dd = 2 . 5 v, v ddq =2.5v, t a = 0 to 70 c ) parameter value unit note input reference voltage for clock 0.5 * v ddq v input signal maximum peak swing 1.5 v input levels(v ih /v il ) v ref +0.3 1 /v ref -0.3 1 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see load circuit
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL ac timming parameters & specifications (these ac charicteristics were tested on the component) parameter symbol -tca2(ddr266a) -tcb0(ddr266b) -tca0 (ddr200) unit note min max min max min max row cycle time trc 65 65 70 ns refresh row cycle time trfc 75 75 80 ns row active time tras 45 120k 45 120k 48 120k ns ras to cas delay trcd 20 20 20 ns row precharge time trp 20 20 20 ns row active to row active delay trrd 15 15 15 ns write recovery time twr 2 2 2 tck last data in to read command tcdlr 1 1 1 tck col. address to col. address delay tccd 1 1 1 tck clock cycle time cl=2.0 tck 7.5 12 10 12 10 12 ns 5 cl=2.5 7.5 12 7.5 12 ns 5 clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ ck tdqsck -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns output data access time from ck/ ck tac -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data strobe edge to ouput data edge tdqsq - 0.5 - 0.5 - 0.6 ns 5 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres 0 0 0 ns 2 dqs-in hold time twpre 0.25 0.25 0.25 tck dqs falling edge to ck rising-setup time tdss 0.2 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 0.35 tck dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 0.9 1.1 tck address and control input setup time(fast) tis 0.9 0.9 1.1 ns 6 address and control input hold time(fast) tih 0.9 0.9 1.1 ns 6 address and control input setup time(slow) tis 1.0 1.0 1.1 ns 6 address and control input hold time(slow) tih 1.0 1.0 1.1 ns 6 data-out high impedence time from ck/ ck thz -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data-out low impedence time from ck/ ck tlz -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns input slew rate(for input only pins) tsl(i) 0.5 0.5 0.5 v/ns 6 input slew rate(for i/o pins) tsl(io) 0.5 0.5 0.5 v/ns 7 output slew rate(x4,x8) tsl(o) 1.0 4.5 1.0 4.5 1.0 4.5 v/ns 10 output slew rate(x16) tsl (o) 0.7 5 0.7 5 0.7 5 v/ns 10 output slew rate matching ratio(rise to fall) t slmr 0.67 1.5 0.67 1.5 0.67 1.5
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL 1. maximum burst refresh of 8 2. the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on tdqss. 3. the maximum limit for this parameter is not a device limit. the device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. a write command can be applied with t rcd satisfied after this command. 5. for registered dimms, t cl and t ch are 3 45% of the period including both the half period jitter (t jit(hp) ) of the pll and the half period jitter due to crosstalk (t jit (crosstalk) ) on the dimm. parameter symbol -tca2(ddr266a) -tcb0(ddr266b) -tca0 (ddr200) unit note min max min max min max mode register set cycle time tmrd 15 15 16 ns dq & dm setup time to dqs tds 0.5 0.5 0.6 ns 7,8,9 dq & dm hold time to dqs tdh 0.5 0.5 0.6 ns 7,8,9 dq & dm input pulse width tdipw 1.75 1.75 2 ns power down exit time tpdex 7.5 7.5 10 ns exit self refresh to non-read command txsnr 75 75 80 ns 4 exit self refresh to read command txsrd 200 200 200 tck refresh interval time 64mb, 128mb trefi 15.6 15.6 15.6 us 1 256mb 7.8 7.8 7.8 us 1 output dqs valid window tqh thp -tqhs - thp -tqhs - thp -tqhs - ns 5 clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - ns data hold skew factor tqhs 0.75 0.75 0.8 ns dqs write postamble time twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck 3
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL 6. input setup/hold slew rate derating this derating table is used to increase t is /t ih in the case where the input slew rate is below 0.5v/ns. input setup/hold slew rate based on the lesser of ac-ac slew rate and dc-dc slew rate. 7. i/o setup/hold slew rate derating this derating table is used to increase t ds /t dh in the case where the i/o slew rate is below 0.5v/ns. i/o setup/hold slew rate based on the lesser of ac-ac slew rate and dc-dc slew rate. 8. i/o setup/hold plateau derating this derating table is used to increase tds/tdh in the case where the input level is flat below vref 310mv for a duration of up to 2ns. 9. i/o delta rise/fall rate(1/slew-rate) derating this derating table is used to increase t ds /t dh in the case where the dq and dqs slew rates differ. the delta rise/fall rate is calated as 1/slewrate1-1/slewrate2. for example, if slew rate 1 = 5v/ns and slew rate 2 =.4v/ns then the delta rise/fall rate =-0/5ns/v. input s/h slew rate based on larger of ac-ac delta rise/fall rate and dc-dc delta rise/fall rate. 10. this parameter is fir system simulation purpose. it is guranteed by design. input setup/hold slew rate d tis d tih (v/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 i/o setup/hold slew rate d tds d tdh (v/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 0.3 +150 +150 i/o input level d tds d tdh (mv) (ps) (ps) 280 +50 +50 delta rise/fall rate d tds d tdh (ns/v) (ps) (ps) 0 0 0 0.25 +50 +50 0.5 +100 +100 the following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0 v/ns. ck slew rate (single ended) d tih/tis (ps) d tdss/tdsh (ps) d tac/tdqsck (ps) d tlz(min) (ps) d thz(max) (ps) 1.0v/ns 0 0 0 0 0 0.75v/ns +50 +50 +50 -50 +50 0.5v/ns +100 +100 +100 -100 +100
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL parameter symbol -tcb3(ddr333) unit note min max row cycle time trc 60 ns refresh row cycle time trfc 72 ns row active time tras 42 70k ns ras to cas delay trcd 18 ns row precharge time trp 18 ns row active to row active delay trrd 12 ns write recovery time twr 15 ns last data in to read command tcdlr 1 tck clock cycle time cl=2.0 tck 7.5 12 ns 4 cl=2.5 6 12 ns 4 clock high level width tch 0.45 0.55 tck clock low level width tcl 0.45 0.55 tck dqs-out access time from ck/ ck tdqsck -0.6 +0.6 ns output data access time from ck/ ck tac -0.7 +0.7 ns data strobe edge to ouput data edge tdqsq - 0.45 ns 4 read preamble trpre 0.9 1.1 tck read postamble trpst 0.4 0.6 tck ck to valid dqs-in tdqss 0.75 1.25 tck dqs-in setup time twpres 0 ns 2 write preamble twpre 0.25 tck write postamble twpst 0.4 0.6 tck 3 dqs falling edge to ck rising-setup time tdss 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 tck dqs-in high level width tdqsh 0.35 tck dqs-in low level width tdqsl 0.35 tck address and control input setup/hold time (fast slew rate) tis/tih 0.75 ns address and control input setup/hold time (slow slew rate) tis/tih 0.8 ns dq and dm input setup time tds 0.45 ns dq and dm input hold time tdh 0.45 ns data-out high impedence time from ck/ ck thz -0.7 +0.7 ps data-out low impedence time from ck/ ck tlz -0.7 +0.7 ps ac timming parameters & specifications (these ac charicteristics were tested on the component)
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL 1. maximum burst refresh of 8 2. the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on tdqss. 3. the maximum limit for this parameter is not a device limit. the device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. for registered dinns, t cl and t ch are 3 45% of the period including both the half period jitter (t jit(hp) ) of the pll and the half period jitter due to crosstalk (t jit (crosstalk) ) on the dimm. parameter symbol -tcb3(ddr333) unit note min max mode register set cycle time tmrd 12 ns control & address input pulse width (for each input) tipw 2.2 ns dq & dm input pulse width(for each input) tdipw 1.75 ns exit self refresh to non read command txsnr 75 ns exit self refresh to read command txsrd 200 tck refresh interval time 64mb, 128mb trefi 15.6 us 1 256mb 7.8 us 1 output dqs valid window tqh thp-tqhs - ns 4 clock half period thp tclmin or tchmin - ns data hold skew factor tqhs 0.55 ns dqs write postamble time trap trcd or tras min ns 3 auto precharge write recovery + precharge time tdal (twr/tck) + (trp/tck) tck
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL command truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we ba 0,1 a 10 /ap a 11, a 12 a 9 ~ a 0 note register extended mrs h x l l l l op code 1, 2 register mode register set h x l l l l op code 1, 2 refresh auto refresh h h l l l h x 3 self refresh entry l 3 exit l h l h h h x 3 h x x x 3 bank active & row addr. h x l l h h v row address read & column address auto precharge disable h x l h l h v l column address (a 0 ~a 9 ) 4 auto precharge enable h 4 write & column address auto precharge disable h x l h l l v l column address (a 0 ~a 9 ) 4 auto precharge enable h 4, 6 burst stop h x l h h l x 7 precharge bank selection h x l l h l v l x all banks x h 5 active power down entry h l h x x x x l v v v exit l h x x x x precharge power down mode entry h l h x x x x l h h h exit l h h x x x l v v v dm h x x 8 no op eration (nop) : not defined h x h x x x x 9 l h h h 9 note : 1. op code : operand code. a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2. emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if both ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if both ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency is 0). 9. this combination is not defined for any function, which means "no operation(nop)" in ddr sdram.
184pin unbuffered ddr sdram module rev. 0.1 nov. 2001 M368L3223CTL tolerances : 0.005(.13) unless otherwise specified. the used device is 32mx8 sdram, tsop. sdram part no : k4h560838c-tc package dimensions 5.25 0.006 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0 . 1 0 0 m i n ( 2 . 3 0 m i n ) 0 . 3 9 3 ( 1 0 . 0 0 ) (1.270 ) 0 . 1 0 0 ( 2 . 5 0 ) detail b a b (128.950) (133.350 0.15 ) 0.250 (6.350 ) detail a 0.157 (4.00 ) 0.071 (1.8 0) 0.039 0.002 (1.000 0. 050) (3.80) 2.175 (6.62) (64.77) (49.53) ( 1 7 . 8 0 ) 2.55 1.95 0.26 2.500 0 . 7 0.10 m c b a 0.10 m c b a m 0.1496 (3.00) 0.118 r (2.00) 0.0787 (4.00) 0.1575 1.25 0.006 (31.75 0.15) ( 4 . 0 0 ) ( 2 x ) 0 . 1 5 7 (3.00) 0.118 0.07 max 0.050 0.0039 (1.270 0.10) (1.20 max)

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